#ifndef _SCL_REG_H_
#define _SCL_REG_H_


// #define REG_VPSS_V_BASE 0x68080000
// #define REG_VPSS_T1_BASE 0x23020000
// #define REG_VPSS_T2_BASE 0x24020000
// #define REG_VPSS_D_BASE 0x67010000
#define REG_TOP_RESET_BASE 0x28103000
#define REG_VI_STS_BASE 0x680be000
#define REG_VO_SYS_BASE 0x67000000
#define REG_VPSS_BASE(x) (x < 4 ? reg_base_vi : (x < 6 ? reg_base_vd0 : (x < 8 ? reg_base_vd1 : reg_base_vo)))
#define REG_VPSS_IP_IDX(x) (x < 4 ? x : (x < 6 ? (x - 4) : (x < 8 ? (x - 6) : (x - 8))))
#define REG_VPSS_SIZE(x) ((x < 4 || x > 7) ? 0X4000 : 0X10000)

#define REG_TOP_OFFSET 0X0
#define REG_CMDQ_OFFSET 0X1000
#define REG_IMG_OFFSET 0X1400
#define REG_CORE_OFFSET 0X1800
#define REG_GOP0_OFFSET 0x1E00
#define REG_GOP1_OFFSET 0x2000
#define REG_ODMA_OFFSET 0X2400
#define REG_FBD_OFFSET 0X2800


#define REG_SCL_TOP_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_TOP_OFFSET)
#define REG_SCL_CMDQ_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_CMDQ_OFFSET)
#define REG_SCL_IMG_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_IMG_OFFSET)
#define REG_SCL_CORE_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_CORE_OFFSET)
#define REG_SCL_GOP0_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_GOP0_OFFSET)
#define REG_SCL_GOP1_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_GOP1_OFFSET)
#define REG_SCL_ODMA_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_ODMA_OFFSET)
#define REG_SCL_FBD_BASE(x) (REG_VPSS_BASE(x) + REG_VPSS_SIZE(x) * (REG_VPSS_IP_IDX(x)) + REG_FBD_OFFSET)

// ============== TOP ============== //
#define REG_SCL_TOP_CFG0(x) (REG_SCL_TOP_BASE(x) + 0x00)
#define REG_SCL_TOP_CFG1(x) (REG_SCL_TOP_BASE(x) + 0x04)
#define REG_SCL_TOP_AXI(x) (REG_SCL_TOP_BASE(x) + 0x08)
#define REG_SCL_TOP_SHD(x) (REG_SCL_TOP_BASE(x) + 0x10)
#define REG_SCL_TOP_DUMMY(x) (REG_SCL_TOP_BASE(x) + 0x14)
#define REG_SCL_TOP_RO_DUMMY(x) (REG_SCL_TOP_BASE(x) + 0x18)
#define REG_SCL_TOP_INTR_MASK(x) (REG_SCL_TOP_BASE(x) + 0x30)
#define REG_SCL_TOP_INTR_STATUS(x) (REG_SCL_TOP_BASE(x) + 0x34)
#define REG_SCL_TOP_INTR_ENABLE(x) (REG_SCL_TOP_BASE(x) + 0x38)
#define REG_SCL_TOP_TRIG_NUM(x) (REG_SCL_TOP_BASE(x) + 0x3C)
#define REG_SCL_TOP_IMG_CTRL(x) (REG_SCL_TOP_BASE(x) + 0x40)
#define REG_SCL_TOP_CMDQ_START(x) (REG_SCL_TOP_BASE(x) + 0x44)
#define REG_SCL_TOP_CMDQ_STOP(x) (REG_SCL_TOP_BASE(x) + 0x48)
#define REG_SCL_TOP_PG(x) (REG_SCL_TOP_BASE(x) + 0x4C)
#define REG_SCL_TOP_SC_074(x) (REG_SCL_TOP_BASE(x) + 0x74)
#define REG_SCL_TOP_SC_078(x) (REG_SCL_TOP_BASE(x) + 0x78)
#define REG_SCL_TOP_SRC_SHARE(x) (REG_SCL_TOP_BASE(x) + 0xcc)
#define REG_SCL_TOP_STITCHING_PATH(x) (REG_SCL_TOP_BASE(x) + 0xc8)
#define REG_SCL_TOP_FBD_HIGNDDR(x) (REG_SCL_TOP_BASE(x) + 0xd0)

// ============== IMG ============== //
#define REG_SCL_IMG_CFG(x) (REG_SCL_IMG_BASE(x) + 0x00)
#define REG_SCL_IMG_OFFSET(x) (REG_SCL_IMG_BASE(x) + 0x04)
#define REG_SCL_IMG_SIZE(x) (REG_SCL_IMG_BASE(x) + 0x08)
#define REG_SCL_IMG_PITCH_Y(x) (REG_SCL_IMG_BASE(x) + 0x0C)
#define REG_SCL_IMG_PITCH_C(x) (REG_SCL_IMG_BASE(x) + 0x10)
#define REG_SCL_IMG_SHD(x) (REG_SCL_IMG_BASE(x) + 0x14)
#define REG_SCL_IMG_ADDR0_L(x) (REG_SCL_IMG_BASE(x) + 0x24)
#define REG_SCL_IMG_ADDR0_H(x) (REG_SCL_IMG_BASE(x) + 0x28)
#define REG_SCL_IMG_ADDR1_L(x) (REG_SCL_IMG_BASE(x) + 0x2C)
#define REG_SCL_IMG_ADDR1_H(x) (REG_SCL_IMG_BASE(x) + 0x30)
#define REG_SCL_IMG_ADDR2_L(x) (REG_SCL_IMG_BASE(x) + 0x34)
#define REG_SCL_IMG_ADDR2_H(x) (REG_SCL_IMG_BASE(x) + 0x38)
#define REG_SCL_IMG_CSC_COEF0(x) (REG_SCL_IMG_BASE(x) + 0x40)
#define REG_SCL_IMG_CSC_COEF1(x) (REG_SCL_IMG_BASE(x) + 0x44)
#define REG_SCL_IMG_CSC_COEF2(x) (REG_SCL_IMG_BASE(x) + 0x48)
#define REG_SCL_IMG_CSC_COEF3(x) (REG_SCL_IMG_BASE(x) + 0x4C)
#define REG_SCL_IMG_CSC_COEF4(x) (REG_SCL_IMG_BASE(x) + 0x50)
#define REG_SCL_IMG_CSC_COEF5(x) (REG_SCL_IMG_BASE(x) + 0x54)
#define REG_SCL_IMG_CSC_SUB(x) (REG_SCL_IMG_BASE(x) + 0x58)
#define REG_SCL_IMG_CSC_ADD(x) (REG_SCL_IMG_BASE(x) + 0x5C)
#define REG_SCL_IMG_FIFO_THR(x) (REG_SCL_IMG_BASE(x) + 0x60)
#define REG_SCL_IMG_OUTSTANDING(x) (REG_SCL_IMG_BASE(x) + 0x64)
#define REG_SCL_IMG_DBG(x) (REG_SCL_IMG_BASE(x) + 0x68)
#define REG_SCL_IMG_AXI_ST(x) (REG_SCL_IMG_BASE(x) + 0x70)
#define REG_SCL_IMG_BW_LIMIT(x) (REG_SCL_IMG_BASE(x) + 0x74)
#define REG_SCL_IMG_CATCH(x) (REG_SCL_IMG_BASE(x) + 0x80)
#define REG_SCL_IMG_CHECKSUM0(x) (REG_SCL_IMG_BASE(x) + 0x84)
#define REG_SCL_IMG_CHECKSUM1(x) (REG_SCL_IMG_BASE(x) + 0x88)
#define REG_SCL_IMG_SB_REG_CTRL(x) (REG_SCL_IMG_BASE(x) + 0x90)
#define REG_SCL_IMG_SB_REG_C_STAT(x) (REG_SCL_IMG_BASE(x) + 0x94)
#define REG_SCL_IMG_SB_REG_Y_STAT(x) (REG_SCL_IMG_BASE(x) + 0x98)
#define REG_SCL_IMG_DUP2FANCY(x) (REG_SCL_IMG_BASE(x) + 0x9c)


// ============== SCL ============== //
// SCL
#define REG_SCL_CFG(x) (REG_SCL_CORE_BASE(x) + 0x00)
#define REG_SCL_SHD(x) (REG_SCL_CORE_BASE(x) + 0x04)
#define REG_SCL_STATUS(x) (REG_SCL_CORE_BASE(x) + 0x08)
#define REG_SCL_SRC_SIZE(x) (REG_SCL_CORE_BASE(x) + 0x0c)
#define REG_SCL_CROP_OFFSET(x) (REG_SCL_CORE_BASE(x) + 0x10)
#define REG_SCL_CROP_SIZE(x) (REG_SCL_CORE_BASE(x) + 0x14)
#define REG_SCL_CORE_CFG(x) (REG_SCL_CORE_BASE(x) + 0x40)
#define REG_SCL_2TAP_CFG(x) (REG_SCL_CORE_BASE(x) + 0x44)
#define REG_SCL_2TAP_NOR(x) (REG_SCL_CORE_BASE(x) + 0x48)
#define REG_SCL_2TAP_DBG(x) (REG_SCL_CORE_BASE(x) + 0x4c)
#define REG_SCL_CHECKSUM0(x) (REG_SCL_CORE_BASE(x) + 0x90)
#define REG_SCL_CHECKSUM1(x) (REG_SCL_CORE_BASE(x) + 0x94)
#define REG_SCL_CHECKSUM2(x) (REG_SCL_CORE_BASE(x) + 0x98)
#define REG_SCL_CHECKSUM3(x) (REG_SCL_CORE_BASE(x) + 0x9c)
#define REG_SCL_COEF0(x) (REG_SCL_CORE_BASE(x) + 0x118)
#define REG_SCL_COEF1(x) (REG_SCL_CORE_BASE(x) + 0x11C)
#define REG_SCL_COEF2(x) (REG_SCL_CORE_BASE(x) + 0x120)
#define REG_SCL_COEF3(x) (REG_SCL_CORE_BASE(x) + 0x124)
#define REG_SCL_COEF4(x) (REG_SCL_CORE_BASE(x) + 0x128)
#define REG_SCL_COEF5(x) (REG_SCL_CORE_BASE(x) + 0x12C)
#define REG_SCL_COEF6(x) (REG_SCL_CORE_BASE(x) + 0x130)
#define REG_SCL_SC_CFG(x) (REG_SCL_CORE_BASE(x) + 0x134)
#define REG_SCL_SC_H_CFG(x) (REG_SCL_CORE_BASE(x) + 0x138)
#define REG_SCL_SC_V_CFG(x) (REG_SCL_CORE_BASE(x) + 0x13C)
#define REG_SCL_OUT_SIZE(x) (REG_SCL_CORE_BASE(x) + 0x140)
#define REG_SCL_SC_H_INI_PH(x) (REG_SCL_CORE_BASE(x) + 0x148)
#define REG_SCL_SC_V_INI_PH(x) (REG_SCL_CORE_BASE(x) + 0x14c)

// CIRCLE
#define REG_SCL_CIR_CFG(x) (REG_SCL_CORE_BASE(x) + 0x200)
#define REG_SCL_CIR_CENTER_X(x) (REG_SCL_CORE_BASE(x) + 0x204)
#define REG_SCL_CIR_CENTER_Y(x) (REG_SCL_CORE_BASE(x) + 0x208)
#define REG_SCL_CIR_RADIUS(x) (REG_SCL_CORE_BASE(x) + 0x20C)
#define REG_SCL_CIR_SIZE(x) (REG_SCL_CORE_BASE(x) + 0x210)
#define REG_SCL_CIR_OFFSET(x) (REG_SCL_CORE_BASE(x) + 0x214)
#define REG_SCL_CIR_COLOR(x) (REG_SCL_CORE_BASE(x) + 0x218)

// COVER
#define REG_SCL_COVER_CFG(x, y) (REG_SCL_CORE_BASE(x) + 0x280 + 0xc * (y))
#define REG_SCL_COVER_SIZE(x, y) (REG_SCL_CORE_BASE(x) + 0x284 + 0xc * (y))
#define REG_SCL_COVER_COLOR(x, y) (REG_SCL_CORE_BASE(x) + 0x288 + 0xc * (y))

// Privacy mask
#define REG_SCL_PRI_CFG(x) (REG_SCL_CORE_BASE(x) + 0x300)
#define REG_SCL_PRI_START(x) (REG_SCL_CORE_BASE(x) + 0x304)
#define REG_SCL_PRI_END(x) (REG_SCL_CORE_BASE(x) + 0x308)
#define REG_SCL_PRI_ALPHA(x) (REG_SCL_CORE_BASE(x) + 0x30C)
#define REG_SCL_PRI_MAP_ADDR_L(x) (REG_SCL_CORE_BASE(x) + 0x310)
#define REG_SCL_PRI_MAP_ADDR_H(x) (REG_SCL_CORE_BASE(x) + 0x314)
#define REG_SCL_PRI_MAP_AXI_CFG(x) (REG_SCL_CORE_BASE(x) + 0x318)
#define REG_SCL_PRI_GRID_CFG(x) (REG_SCL_CORE_BASE(x) + 0x31C)
#define REG_SCL_PRI_DBG(x) (REG_SCL_CORE_BASE(x) + 0x320)

//border vpp
#define REG_SCL_BORDER_VPP_OFFSET (0x14)
#define REG_SCL_BORDER_VPP_CFG(x, y) (REG_SCL_CORE_BASE(x) + 0x324 + REG_SCL_BORDER_VPP_OFFSET * (y))
#define REG_SCL_BORDER_VPP_INX(x, y) (REG_SCL_CORE_BASE(x) + 0x328 + REG_SCL_BORDER_VPP_OFFSET * (y))
#define REG_SCL_BORDER_VPP_INY(x, y) (REG_SCL_CORE_BASE(x) + 0x32c + REG_SCL_BORDER_VPP_OFFSET * (y))
#define REG_SCL_BORDER_VPP_OUTX(x, y) (REG_SCL_CORE_BASE(x) + 0x330 + REG_SCL_BORDER_VPP_OFFSET * (y))
#define REG_SCL_BORDER_VPP_OUTY(x, y) (REG_SCL_CORE_BASE(x) + 0x334 + REG_SCL_BORDER_VPP_OFFSET * (y))

// GOP0
#define REG_SCL_GOP0_FMT(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x00)
#define REG_SCL_GOP0_H_RANGE(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x04)
#define REG_SCL_GOP0_V_RANGE(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x08)
#define REG_SCL_GOP0_ADDR_L(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x0c)
#define REG_SCL_GOP0_ADDR_H(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x10)
#define REG_SCL_GOP0_CROP_PITCH(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x14)
#define REG_SCL_GOP0_SIZE(x, y) (REG_SCL_GOP0_BASE(x) + 0x20*y + 0x18)
#define REG_SCL_GOP0_CFG(x) (REG_SCL_GOP0_BASE(x) + 0x100)
#define REG_SCL_GOP0_256LUT0(x) (REG_SCL_GOP0_BASE(x) + 0x104)
#define REG_SCL_GOP0_256LUT1(x) (REG_SCL_GOP0_BASE(x) + 0x108)
#define REG_SCL_GOP0_COLORKEY(x) (REG_SCL_GOP0_BASE(x) + 0x10c)
#define REG_SCL_GOP0_FONTCOLOR(x) (REG_SCL_GOP0_BASE(x) + 0x110)
#define REG_SCL_GOP0_FONTCOLOR_INV(x) (REG_SCL_GOP0_BASE(x) + 0x118)
#define REG_SCL_GOP0_BUSY(x) (REG_SCL_GOP0_BASE(x) + 0x11c)
#define REG_SCL_GOP0_FONTBOX_CTRL(x) (REG_SCL_GOP0_BASE(x) + 0x120)
#define REG_SCL_GOP0_FONTBOX_CFG(x, y) (REG_SCL_GOP0_BASE(x) + 0x10*y + 0x124)
#define REG_SCL_GOP0_FONTBOX_INIT(x, y) (REG_SCL_GOP0_BASE(x) + 0x10*y + 0x128)
#define REG_SCL_GOP0_FONTBOX_REC(x, y) (REG_SCL_GOP0_BASE(x) + 0x10*y + 0x12c)
#define REG_SCL_GOP0_BW_LIMIT(x) (REG_SCL_GOP0_BASE(x) + 0x140)
#define REG_SCL_GOP0_LV2(x) (REG_SCL_GOP0_BASE(x) + 0x144)
#define REG_SCL_GOP0_LV2_PARA(x) (REG_SCL_GOP0_BASE(x) + 0x148)
#define REG_SCL_GOP0_DEC_CTRL(x) (REG_SCL_GOP0_BASE(x) + 0x150)
#define REG_SCL_GOP0_DEC_DEBUG(x) (REG_SCL_GOP0_BASE(x) + 0x154)
#define REG_SCL_GOP0_16LUT(x, y) (REG_SCL_GOP0_BASE(x) + 0x2*y + 0x160)

// GOP1
#define REG_SCL_GOP1_FMT(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x00)
#define REG_SCL_GOP1_H_RANGE(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x04)
#define REG_SCL_GOP1_V_RANGE(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x08)
#define REG_SCL_GOP1_ADDR_L(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x0c)
#define REG_SCL_GOP1_ADDR_H(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x10)
#define REG_SCL_GOP1_CROP_PITCH(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x14)
#define REG_SCL_GOP1_SIZE(x, y) (REG_SCL_GOP1_BASE(x) + 0x20*y + 0x18)
#define REG_SCL_GOP1_CFG(x) (REG_SCL_GOP1_BASE(x) + 0x100)
#define REG_SCL_GOP1_256LUT0(x) (REG_SCL_GOP1_BASE(x) + 0x104)
#define REG_SCL_GOP1_256LUT1(x) (REG_SCL_GOP1_BASE(x) + 0x108)
#define REG_SCL_GOP1_COLORKEY(x) (REG_SCL_GOP1_BASE(x) + 0x10c)
#define REG_SCL_GOP1_FONTCOLOR(x) (REG_SCL_GOP1_BASE(x) + 0x110)
#define REG_SCL_GOP1_FONTCOLOR_INV(x) (REG_SCL_GOP1_BASE(x) + 0x118)
#define REG_SCL_GOP1_BUSY(x) (REG_SCL_GOP1_BASE(x) + 0x11c)
#define REG_SCL_GOP1_FONTBOX_CTRL(x) (REG_SCL_GOP1_BASE(x) + 0x120)
#define REG_SCL_GOP1_FONTBOX_CFG(x, y) (REG_SCL_GOP1_BASE(x) + 0x10*y + 0x124)
#define REG_SCL_GOP1_FONTBOX_INIT(x, y) (REG_SCL_GOP1_BASE(x) + 0x10*y + 0x128)
#define REG_SCL_GOP1_FONTBOX_REC(x, y) (REG_SCL_GOP1_BASE(x) + 0x10*y + 0x12c)
#define REG_SCL_GOP1_BW_LIMIT(x) (REG_SCL_GOP1_BASE(x) + 0x140)
#define REG_SCL_GOP1_LV2(x) (REG_SCL_GOP1_BASE(x) + 0x144)
#define REG_SCL_GOP1_LV2_PARA(x) (REG_SCL_GOP1_BASE(x) + 0x148)
#define REG_SCL_GOP1_DEC_CTRL(x) (REG_SCL_GOP1_BASE(x) + 0x150)
#define REG_SCL_GOP1_DEC_DEBUG(x) (REG_SCL_GOP1_BASE(x) + 0x154)
#define REG_SCL_GOP1_16LUT(x, y) (REG_SCL_GOP1_BASE(x) + 0x2*y + 0x160)

// BORDER
#define REG_SCL_BORDER_CFG(x) (REG_SCL_CORE_BASE(x) + 0x80)
#define REG_SCL_BORDER_OFFSET(x) (REG_SCL_CORE_BASE(x) + 0x84)

// ODMA
#define REG_SCL_ODMA_CFG(x) (REG_SCL_ODMA_BASE(x) + 0x00)
#define REG_SCL_ODMA_ADDR0_L(x) (REG_SCL_ODMA_BASE(x) + 0x04)
#define REG_SCL_ODMA_ADDR0_H(x) (REG_SCL_ODMA_BASE(x) + 0x08)
#define REG_SCL_ODMA_ADDR1_L(x) (REG_SCL_ODMA_BASE(x) + 0x0C)
#define REG_SCL_ODMA_ADDR1_H(x) (REG_SCL_ODMA_BASE(x) + 0x10)
#define REG_SCL_ODMA_ADDR2_L(x) (REG_SCL_ODMA_BASE(x) + 0x14)
#define REG_SCL_ODMA_ADDR2_H(x) (REG_SCL_ODMA_BASE(x) + 0x18)
#define REG_SCL_ODMA_PITCH_Y(x) (REG_SCL_ODMA_BASE(x) + 0x1C)
#define REG_SCL_ODMA_PITCH_C(x) (REG_SCL_ODMA_BASE(x) + 0x20)
#define REG_SCL_ODMA_OFFSET_X(x) (REG_SCL_ODMA_BASE(x) + 0x24)
#define REG_SCL_ODMA_OFFSET_Y(x) (REG_SCL_ODMA_BASE(x) + 0x28)
#define REG_SCL_ODMA_WIDTH(x) (REG_SCL_ODMA_BASE(x) + 0x2C)
#define REG_SCL_ODMA_HEIGHT(x) (REG_SCL_ODMA_BASE(x) + 0x30)
#define REG_SCL_ODMA_DBG(x) (REG_SCL_ODMA_BASE(x) + 0x34)
#define REG_SCL_ODMA_LATCH_LINE_CNT(x) (REG_SCL_ODMA_BASE(x) + 0x40)
#define REG_SCL_ODMA_SB_CTRL(x) (REG_SCL_ODMA_BASE(x) + 0x50)

// CSC
#define REG_SCL_CSC_EN(x) (REG_SCL_ODMA_BASE(x) + 0x100)
#define REG_SCL_CSC_COEF0(x) (REG_SCL_ODMA_BASE(x) + 0x104)
#define REG_SCL_CSC_COEF1(x) (REG_SCL_ODMA_BASE(x) + 0x108)
#define REG_SCL_CSC_COEF2(x) (REG_SCL_ODMA_BASE(x) + 0x10c)
#define REG_SCL_CSC_COEF3(x) (REG_SCL_ODMA_BASE(x) + 0x110)
#define REG_SCL_CSC_COEF4(x) (REG_SCL_ODMA_BASE(x) + 0x114)
#define REG_SCL_CSC_OFFSET(x) (REG_SCL_ODMA_BASE(x) + 0x118)
#define REG_SCL_CSC_FRAC0(x) (REG_SCL_ODMA_BASE(x) + 0x11C)
#define REG_SCL_CSC_FRAC1(x) (REG_SCL_ODMA_BASE(x) + 0x120)

//convert to
#define REG_SCL_CONVERT_TO_A0(x) (REG_SCL_ODMA_BASE(x) + 0x124)
#define REG_SCL_CONVERT_TO_A1(x) (REG_SCL_ODMA_BASE(x) + 0x128)
#define REG_SCL_CONVERT_TO_A2(x) (REG_SCL_ODMA_BASE(x) + 0x12c)
#define REG_SCL_CONVERT_TO_B0(x) (REG_SCL_ODMA_BASE(x) + 0x130)
#define REG_SCL_CONVERT_TO_B1(x) (REG_SCL_ODMA_BASE(x) + 0x134)
#define REG_SCL_CONVERT_TO_B2(x) (REG_SCL_ODMA_BASE(x) + 0x138)

//fbd
#define REG_SCL_MAP_CONV_CTRL(x) (REG_SCL_FBD_BASE(x) + 0x00)
#define REG_SCL_MAP_CONV_STATUS(x) (REG_SCL_FBD_BASE(x) + 0x04)
#define REG_SCL_MAP_CONV_OFF_BASE_Y(x) (REG_SCL_FBD_BASE(x) + 0x08)
#define REG_SCL_MAP_CONV_OFF_BASE_C(x) (REG_SCL_FBD_BASE(x) + 0x0C)
#define REG_SCL_MAP_CONV_OFF_STRIDE(x) (REG_SCL_FBD_BASE(x) + 0x10)
#define REG_SCL_MAP_CONV_COMP_BASE_Y(x) (REG_SCL_FBD_BASE(x) + 0x14)
#define REG_SCL_MAP_CONV_COMP_BASE_C(x) (REG_SCL_FBD_BASE(x) + 0x18)
#define REG_SCL_MAP_CONV_COMP_STRIDE(x) (REG_SCL_FBD_BASE(x) + 0x1C)
#define REG_SCL_MAP_CONV_CROP_POS(x) (REG_SCL_FBD_BASE(x) + 0x20)
#define REG_SCL_MAP_CONV_CROP_SIZE(x) (REG_SCL_FBD_BASE(x) + 0x24)
#define REG_SCL_MAP_CONV_OUT_CTRL(x) (REG_SCL_FBD_BASE(x) + 0x28)
#define REG_SCL_MAP_CONV_TIME_OUT(x) (REG_SCL_FBD_BASE(x) + 0x2c)
#define REG_SCL_MAP_CONV_ENDIAN(x) (REG_SCL_FBD_BASE(x) + 0x30)
#define REG_SCL_MAP_CONV_BIT_DEPTH(x) (REG_SCL_FBD_BASE(x) + 0x34)

#endif  // _SCL_REG_H_
